HIGH Introduced in 5.18
perf CounterMask OOB
CVE-2026-97587
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:L
01Description
In the Linux kernel, the following vulnerability has been resolved: perf: RISC-V: store available counter mask as bitmap The available-counter mask was a single unsigned long, but iteration uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object. Filling with an unsigned-long bit at index 32 and above is also wrong. Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word into CFG_MATCH when checking events, when allocating an index, and when stopping all counters. Set the counter base to i times BITS_PER_LONG. Share the CFG_MATCH ecall through a small helper so the 32-bit argument split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits above XLEN set, so the first word alone is not enough. [pjw@kernel.org: updated to apply; fixed checkpatch.pl issues]
02KernelScan AI Analysis
Risk summary
Any local user on a 32-bit RISC-V system with the SBI PMU extension can trigger out-of-bounds memory access through the perf subsystem, potentially leaking or corrupting kernel memory. The bug also causes automatic memory corruption at boot when firmware reports counters with indices at or above 32. 64-bit RISC-V systems are unaffected.
Vulnerability analysis
The RISC-V performance monitoring driver stores its available counter mask in a single word, but on 32-bit RISC-V this holds only 32 bits while the code iterates over 64 possible counter indices. When a local user opens a perf event, the driver reads past the end of the mask variable to test or iterate counter bits, accessing adjacent kernel memory. During device initialization, the driver also writes past the end of the variable when recording counters with indices at or above 32, corrupting adjacent memory. The fix replaces the single word with a proper multi-word bitmap and uses bitmap helper functions throughout so all 64 counter slots are handled correctly on both 32-bit and 64-bit systems. The vulnerable path is reachable from any local user on an affected 32-bit RISC-V system with the SBI PMU extension; the write corruption occurs automatically at boot when firmware reports high-numbered counters.
Lifecycle
03Fix Versions
| Branch | Introduced | Fixed in | Patch commit |
|---|---|---|---|
| 6.12 | 5.18 | 6.12.111 | 143668c42477 |
| 6.18 | 5.18 | 6.18.53 | 9bec7beaed07 |
| 7.2 | 5.18 | 7.2.7 | e5481db31f46 |
| mainline | 5.18 | 7.3-rc3 | 6809da6e9c08 |
| cip/6.12 | 5.18 | 6.12.111-cip32 | 143668c42477 |