HIGH Introduced in 4.7
xilinx_dma ChannelIdle Race
CVE-2026-93170
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
KernelScan AI6.9MEDIUM
01Description
In the Linux kernel, the following vulnerability has been resolved: dmaengine: xilinx_dma: Fix channel idle state management in AXIDMA and MCDMA interrupt handlers Fix a race condition in AXIDMA and MCDMA irq handlers where the channel could be incorrectly marked as idle and attempt spurious transfers when descriptors are still being processed. The issue occurs when: 1. Multiple descriptors are queued and active. 2. An interrupt fires after completing some descriptors. 3. xilinx_dma_complete_descriptor() moves completed descriptors to done_list. 4. Channel is marked idle and start_transfer() is called even though active_list still contains unprocessed descriptors. 5. This leads to premature transfer attempts and potential descriptor corruption or missed completions. Only mark the channel as idle and start new transfers when the active list is actually empty, ensuring proper channel state management and avoiding spurious transfer attempts.
02KernelScan AI Analysis
Risk summary
A race condition in the Xilinx AXI DMA and MCDMA interrupt handlers can cause a DMA channel to be prematurely marked idle while descriptors are still active, leading to spurious transfer attempts and potential descriptor corruption. The bug requires Xilinx DMA hardware (a soft IP core on Xilinx FPGA platforms) and a local actor who can submit multiple DMA descriptors. Exploitation is timing-dependent; corrupted DMA state can compromise data confidentiality and integrity as well as destabilize the system.
Vulnerability analysis
In the Xilinx AXI DMA and MCDMA interrupt handlers, the channel is unconditionally marked idle and a new transfer is started after completing some descriptors, even when other descriptors are still being processed. When an interrupt fires after partial completion, this causes the driver to attempt spurious transfers against descriptors still in flight, which can corrupt the descriptor chain or cause missed completions. The fix adds a check so the channel is only marked idle and new transfers are only started when all outstanding descriptors have finished. This vulnerability is reachable only on systems with Xilinx DMA hardware and requires a local user or service that submits multiple queued DMA transfers; the race window depends on interrupt timing relative to descriptor processing.
Lifecycle
03Fix Versions
| Branch | Introduced | Fixed in | Patch commit |
|---|---|---|---|
| 5.15 | 4.7 | 5.15.221 | 5459e02707b2 |
| 6.1 | 4.7 | 6.1.188 | 425630e9eea1 |
| 6.6 | 4.7 | 6.6.157 | fdaf297ab275 |
| 6.12 | 4.7 | 6.12.110 | c27d16fd2358 |
| 6.18 | 4.7 | 6.18.52 | ec927657524b |
| 7.2 | 4.7 | 7.2.6 | c3e943490ced |
| mainline | 4.7 | 7.3-rc1 | 0b6d055edb55 |
| 5.10 | 4.7 | 5.10.270 | 7f4b989d7d87 |
| cip/6.12 | 4.7 | 6.12.111-cip32 | c27d16fd2358 |