HIGH Introduced in 6.17
iommu Vintf Race
CVE-2026-90429
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
KernelScan AI6.9MEDIUM
01Description
In the Linux kernel, the following vulnerability has been resolved: iommu/tegra241-cmdqv: Synchronize the error ISR against VINTF (de)init A user VINTF is torn down by tegra241_cmdqv_deinit_vintf(), which runs from the destroy callback and from the init-failure unwind in the alloc handler. It clears the cmdqv->vintfs[] slot and lets the iommufd core free it, but nothing serializes that against the error interrupt: tegra241_cmdqv_isr() reads cmdqv->vintfs[idx] and dereferences the vintf. A concurrent error can make the ISR read a slot mid-clear (a NULL deref) or use a vintf which is about to be freed (a use-after-free). deinit_vintf() also returns idx to the IDA before clearing the slot, so a concurrent create that reuses idx can publish its new vintf into the slot, only for this teardown to erase it again with the stale NULL store. On the other end, tegra241_cmdqv_init_vintf() publishes a new vintf with a plain store to the cmdqv->vintfs[] slot, and the ISR dereferences fields of a published vintf such as vintf->base. A plain store gives no ordering on a weakly-ordered CPU, and a stale VINTF_ERR_MAP bit on a reused idx can make the ISR pick a vintf the moment it is published, before its fields are set or tegra241_vintf_hw_init() runs. The cmdqv->vintfs[0] slot stays NULL until tegra241_cmdqv_init_structures() first creates VINTF0, so the slot 0 read needs the same NULL check. Publish every slot with an smp_store_release(), and read each slot in the ISR with an smp_load_acquire() under a NULL check, so the ISR always sees a fully built vintf or NULL. Also make deinit_vintf() clear the slot, and synchronize_irq() prior to returning idx to the IDA, so no vintf is freed under a running handler and no reused idx is clobbered.
02KernelScan AI Analysis
Risk summary
A race condition in the NVIDIA Tegra241 CMDQV IOMMU driver lets a concurrent hardware error interrupt dereference a virtual interface slot that is being created or destroyed, causing a NULL dereference or use-after-free in the host kernel. The driver is specific to NVIDIA Grace CPUs and is reached locally through the iommufd interface, typically by a virtual machine monitor managing interfaces for guest VMs. A successful exploit can crash the kernel or corrupt kernel memory, and a malicious guest can trigger the error interrupts that race against host-side management operations.
Vulnerability analysis
The NVIDIA Tegra241 CMDQV IOMMU driver's error interrupt handler reads virtual interface slots without synchronizing against the code that creates and destroys them. A concurrent hardware error can fire while an interface is being torn down, causing the handler to dereference a slot that has already been cleared (a NULL dereference) or to access an interface object that is about to be freed (a use-after-free). The teardown also returns the slot index to the allocator before clearing the slot, so a concurrent create can reuse the index and have its freshly published interface erased by the stale teardown; on weakly-ordered CPUs the plain store used to publish a new interface gives no ordering guarantee, letting the handler observe a partially initialized object. The fix ensures proper memory ordering when publishing and reading slots, adds a NULL check in the handler, and makes teardown clear the slot and wait for any in-flight interrupt before returning the index for reuse. This driver is specific to NVIDIA Grace CPUs and is reached through the iommufd interface by a local process, typically a virtual machine monitor managing interfaces for guest VMs; a malicious guest can trigger the hardware error interrupts that race against the host-side create and destroy operations.
Lifecycle
03Fix Versions
| Branch | Introduced | Fixed in | Patch commit |
|---|---|---|---|
| 6.18 | 6.17 | 6.18.52 | bcb82407633c |
| mainline | 6.17 | 7.3-rc1 | a491be376abd |
| 7.2 | 6.17 | 7.2.6 | f3ef4abc271a |