HIGH Introduced in 4.9
amdgpu ComputeQueue Race
CVE-2026-90286
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H
KernelScan AI7.0HIGH
01Description
In the Linux kernel, the following vulnerability has been resolved: drm/amdgpu/gfx6: Use PFP on the compute queues too On GFX6, the compute rings use the same CP path as the graphics ring. The only difference is that they don't support draw commands. (As opposed to GFX7 and newer which have a separate command parser that is called MEC for compute queues.) This means that we have to take into consideration that the PFP also exists on compute queues on GFX6: Use PFP for register writes on both graphics and compute queues. In the pipeline sync, use the PFP to wait for the previous fence (and not the ME) to prevent the PFP from starting to execute the next submission while the ME is still in the previous submission. After a VM flush, emit PFP_SYNC_ME on compute queues as well.
02KernelScan AI Analysis
Risk summary
A local user with access to an AMD GFX6 (Southern Islands) GPU can trigger a race condition in the GPU command pipeline by submitting compute workloads. The race between the Pre-Fetch Parser and Micro Engine on compute queues can lead to out-of-order execution of VM flushes and register writes, potentially corrupting GPU or system memory. Systems without AMD GFX6 hardware or without local GPU access are not affected.
Vulnerability analysis
On AMD GFX6 GPUs, compute queues share the same command parser hardware path as graphics queues, including the Pre-Fetch Parser (PFP). The driver incorrectly limited PFP usage to graphics queues only, causing compute queues to use the Micro Engine (ME) for pipeline synchronization, VM flushes, and register writes. This allowed the PFP to begin processing the next submission while the ME was still executing the previous one, creating a race condition where VM flushes and register writes could execute out of order—potentially causing the GPU to operate on stale page tables and access or corrupt memory belonging to another process. The fix enables PFP on all GFX6 queue types for register writes, pipeline syncs, and VM flush synchronization, and adjusts the compute ring's frame size to account for the additional synchronization command. A local user with access to the GPU render device node can trigger this vulnerability by submitting compute workloads; no root privileges are required, only membership in the group that owns the DRI device.
Lifecycle
03Fix Versions
| Branch | Introduced | Fixed in | Patch commit |
|---|---|---|---|
| 5.10 | 4.9 | 5.10.270 | f37211b9c014 |
| 5.15 | 4.9 | 5.15.221 | 2aa869c6b23e |
| 6.1 | 4.9 | 6.1.188 | fbabc39b4f0f |
| 6.12 | 4.9 | 6.12.110 | e1d3018e3621 |
| 6.18 | 4.9 | 6.18.52 | 8d752f1bb73f |
| 6.6 | 4.9 | 6.6.157 | b5d1d3e4519d |
| 7.2 | 4.9 | 7.2.6 | e399e9d7e291 |
| mainline | 4.9 | 7.3 | 60f20946cd31 |
| cip/5.10 | 4.9 | 5.10.271-cip78 | f37211b9c014 |
| cip/6.1 | 4.9 | 6.1.189-cip61 | fbabc39b4f0f |
| cip/6.1-rt | 4.9 | 6.1.189-cip61-rt32 | fbabc39b4f0f |
| cip/6.12 | 4.9 | 6.12.111-cip32 | e1d3018e3621 |
04CIP Kernels
State of the newest release of each Civil Infrastructure Platform SLTS tree, from CIP's own fix records.
| CIP tree | State |
|---|---|
| cip/6.12 | Fixed in 6.12.111-cip32 |
| cip/6.1 | Fixed in 6.1.189-cip61 |
| cip/6.1-rt | Fixed in 6.1.189-cip61-rt32 |
| cip/5.10 | Fixed in 5.10.271-cip78 |
| cip/5.10-rt | Affected — no CIP fix yet (latest 5.10.268-cip77-rt34) |
| cip/4.19 | Affected — no CIP fix yet (latest 4.19.325-cip136) |
| cip/4.19-rt | Affected — no CIP fix yet (latest 4.19.325-cip136-rt50) |