HIGH Introduced in 6.12
vt-d ContextEntry Race
CVE-2026-90243
CVSS:3.1/AV:L/AC:H/PR:N/UI:N/S:C/C:H/I:H/A:H
KernelScan AI4.1MEDIUM
01Description
In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Clear Present bit before tearing down copied context entry copied_context_tear_down() zeroes the 128-bit context entry with context_clear_entry() while the Present bit is still set, and only then issues the context-cache and IOTLB invalidations. This leaves a window in which hardware can fetch a torn entry, with some fields already zeroed while Present is still set, leading to unpredictable behaviour or spurious faults. While x86 provides strong write ordering, the compiler may reorder the writes to the two 64-bit halves of the entry, and the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes. There is no cacheline flush before the invalidation either, so on an IOMMU without coherent access to the context table the zeroed entry may not be visible to hardware at the point the invalidation is submitted. Apply the same ownership handshake described in the VT-d spec, Section 6.5.3.3 ("Guidance to Software for Invalidations"): clear only the Present bit, flush it out to the IOMMU, perform the invalidations, and only then zero the remainder of the entry.
02KernelScan AI Analysis
Risk summary
A race condition in the Intel VT-d IOMMU driver allows hardware to fetch a partially-written context entry during teardown, because the Present bit is not cleared before zeroing the rest of the entry. This can cause spurious DMA faults or unpredictable IOMMU behavior on systems with Intel VT-d hardware. The issue requires privileged local access to trigger and specific Intel IOMMU hardware.
Vulnerability analysis
During IOMMU context teardown, the driver zeroes the entire context entry while the Present bit remains set. This creates a window where the IOMMU hardware can fetch a torn entry with some fields already cleared but the Present bit still asserted. Compiler reordering of writes and lack of cache flushing on non-coherent IOMMUs widen this window further. The fix follows the VT-d specification's ownership handshake: first clear only the Present bit and flush it to the IOMMU, then issue invalidations, and only then zero the remainder of the entry. This path is reachable only by privileged local operations such as device unbinding or VFIO passthrough teardown on systems with Intel VT-d IOMMU hardware.
Lifecycle
03Fix Versions
| Branch | Introduced | Fixed in | Patch commit |
|---|---|---|---|
| 6.12 | 6.12 | 6.12.110 | 97750a8dce79 |
| 6.18 | 6.12 | 6.18.52 | 3c88cfedc776 |
| 7.2 | 6.12 | 7.2.6 | 6b822d18c33a |
| mainline | 6.12 | 7.3 | f532c57985b1 |
| cip/6.12 | 6.12 | 6.12.111-cip32 | 97750a8dce79 |
04CIP Kernels
State of the newest release of each Civil Infrastructure Platform SLTS tree, from CIP's own fix records.
| CIP tree | State |
|---|---|
| cip/6.12 | Fixed in 6.12.111-cip32 |