HIGH Introduced in 6.9
iommu SmContext UAF
CVE-2026-90241
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:H
KernelScan AI6.4MEDIUM
01Description
In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Tear down scalable-mode context on probe failure intel_pasid_setup_sm_context() walks a PCI device’s DMA aliases via pci_for_each_dma_alias() and programs a scalable-mode context entry for each RID. For a device with a dma_alias_mask, the callback is invoked once for the device’s own RID and once for each alias bit, all with the same pci_dev, so device_pasid_table_setup() runs for multiple RIDs. pci_for_each_dma_alias() stops at the first callback error. Therefore, a failure partway through the walk can leave context entries for already processed RIDs present and still pointing to the device’s PASID table. On this error path, intel_iommu_probe_device() currently jumps directly to intel_pasid_free_table(), which frees the PASID table without first tearing down those context entries. The IOMMU may then walk a present context entry whose PASID table pointer references freed memory. intel_iommu_release_device() already performs teardown before freeing the table. Apply the same ordering on the probe failure path. device_pasid_table_teardown() safely handles RIDs that were never programmed: iommu_context_addr() returns NULL when no context table has been allocated, and clearing the Present bit of an already non-present entry is a no-op. So unwind is safe for both the alias that failed and any aliases not yet reached.
02KernelScan AI Analysis
Risk summary
A use-after-free in the Intel VT-d IOMMU driver occurs when a PCI device probe fails partway through setting up scalable-mode context entries for DMA aliases. The PASID table is freed while context entries still reference it, allowing the IOMMU hardware to access freed memory. This requires local root access or physical PCI hotplug capability and Intel VT-d scalable mode hardware.
Vulnerability analysis
When the Intel VT-d IOMMU driver probes a PCI device that has DMA aliases, it programs a scalable-mode context entry for each alias RID, directing each to the device's PASID table. If this setup fails partway through the alias walk, context entries for already-processed RIDs remain present and still point to the PASID table. The original error path frees the PASID table without first clearing those context entries, leaving the IOMMU hardware with dangling pointers to freed memory — a use-after-free that can lead to memory corruption or a kernel panic when the hardware next walks those entries. The fix inserts a context teardown call before the table free on the error path, matching the ordering already used in the device release path; the teardown helper safely handles RIDs that were never programmed. This vulnerability is reachable only locally: an attacker must either physically hot-plug a PCI device or hold root privileges to trigger a device reprobe via sysfs, and the system must have Intel VT-d scalable mode enabled.
Lifecycle
03Fix Versions
| Branch | Introduced | Fixed in | Patch commit |
|---|---|---|---|
| 6.12 | 6.9 | 6.12.110 | 25ac85a9747c |
| 6.18 | 6.9 | 6.18.52 | d0e978ced742 |
| 7.2 | 6.9 | 7.2.6 | db5daf25f754 |
| mainline | 6.9 | 7.3 | c509fb73a109 |
| cip/6.12 | 6.9 | 6.12.111-cip32 | 25ac85a9747c |
04CIP Kernels
State of the newest release of each Civil Infrastructure Platform SLTS tree, from CIP's own fix records.
| CIP tree | State |
|---|---|
| cip/6.12 | Fixed in 6.12.111-cip32 |