HIGH Introduced in 6.7
cxl RchAer OOB
CVE-2026-89731
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:H
KernelScan AI7.1HIGH
01Description
In the Linux kernel, the following vulnerability has been resolved: cxl/ras: Fix cxl_rch_get_aer_info() out-of-bounds AER register read cxl_rch_get_aer_info() copies the RCH Downstream Port AER capability from the RCRB MMIO block using a readl() loop bounded by sizeof(struct aer_capability_regs). This struct is a software layout and its embedded struct pcie_tlp_log is larger than the on-wire AER capability. As a result the loop reads past the mapped AER register block. The over-read also populates the software-only tail fields including header_log.header_len. An out-of-range header_len passed to pcie_print_tlp_log() can then loop past the header log buffer and cause a second out-of-bounds read. The read was correct when introduced, but struct pcie_tlp_log has since grown (Header Log and TLP Prefix Log sizes, header_len and flit fields), so sizeof(struct aer_capability_regs) no longer matches the physical AER capability. Bound the read to the physical AER registers, header through the 16 byte Header Log. Zero the destination first so the software-only fields are deterministic.
02KernelScan AI Analysis
Risk summary
A local user with access to CXL RCH error handling paths can trigger an out-of-bounds read from RCRB MMIO, potentially leaking kernel memory or causing a kernel panic. The bug is in CXL RCH downstream port AER register handling and requires CXL hardware and driver support.
Vulnerability analysis
The CXL RCH error handler copies AER capability registers from an RCRB MMIO block using a software struct size that is larger than the physical AER capability, causing an out-of-bounds read past the mapped register block. The over-read also populates software-only fields with garbage values, which can drive a second out-of-bounds read when printing TLP log information. The fix bounds the copy to the physically-defined AER registers and zeroes the destination first so software-only fields are deterministic. This is reachable locally on systems with CXL RCH hardware when an AER error triggers the RCH downstream port handler.
Lifecycle
03Fix Versions
| Branch | Introduced | Fixed in | Patch commit |
|---|---|---|---|
| mainline | 6.7 | 7.3-rc1 | 29458e62d082 |
| 6.12 | 6.7 | 6.12.111 | 7f5a2a330dde |
| 6.18 | 6.7 | 6.18.51 | 8bd3523df131 |
| 7.2 | 6.7 | 7.2.4 | 8e3d9dbb25d3 |
| cip/6.12 | 6.7 | 6.12.111-cip32 | 7f5a2a330dde |